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Design And Reuse15h
Analogue Insight and Tetrivis Announce Joint Development of "Eurytion RFK1," a UCIe based 12nm Ka/Ku-Band RF Chiplet Transceiver
As part of this initiative, Analogue Insight and Tetrivis have signed a Memorandum of Understanding (MoU) to jointly develop the chiplet, aligning their IP roadmaps, technology resources, and customer ...
Design And Reuse1d
EnSilica expands satcoms user terminal portfolio with dual-beam, dual-polarization Ku-band analogue beamformer chipset
The ENS92051 is the dual-beam Ku-band receiver (Rx) supporting eight channels with separate amplitude and phase control. The Rx carrier frequency range is 10.7 to 12.75 GHz with an instantaneous ...
Design And Reuse2d
Expedera s Origin Evolution NPU IP Brings Generative AI to Edge Devices
Expedera launches its Origin Evolution NPU IP, bringing hardware acceleration to meet the computational demands of running ...
Design And Reuse1d
GlobalFoundries partners with A*STAR to accelerate advanced packaging innovation
SINGAPORE -- May, 20 2025 – GlobalFoundries (Nasdaq: GFS) (GF) today announced plans to expand its capabilities in advanced packaging through a new Memorandum of Understanding (MOU) signed with the ...
Design And Reuse1d
SiFive Collaborates with Red Hat to Support Red Hat Enterprise Linux for RISC-V
"Native Red Hat Enterprise Linux support on SiFive’s HiFive Premier P550 board offers developers a substantial enterprise-grade toolchain for RISC-V. This is a pivotal step forward in enabling a ...
Design And Reuse1d
The RISC-V World Sees Changes, Milestones, and Innovations
In fifteen years, RISC-V has gone from an academic project at UC Berkeley to one of the major technological trends in compute. The ISA has since flourished in an era that appreciates its royalty-free, ...
Design And Reuse1d
Intel eyes sale of network and edge unit as cost-cutting continues: report
Intel's cost-cutting measures look set to continue as it's reportedly looking to divest its network and edge businesses. Reuters reports that the embattled firm is looking to sideline parts of the ...
Design And Reuse2d
BrainChip CTO to Present on Architectural Innovation for Low-Power AI at the Embedded Vision Summit
Attendees of the Summit can visit BrainChip at booth #716 to see live demonstrations of the company’s latest advancements in Edge AI technology, including innovations in on-chip language processing, ...
Design And Reuse2d
Creonic Adds oFEC Codec IP Core to Portfolio, Expanding High-Speed Networking Solutions for ASIC and FPGA
Creonic GmbH, a leading provider of ready-to-use IP cores for ASIC and FPGA applications, announces the release of its new oFEC (Open Forward Error Correction) codec IP core. The solution supports ...
Design And Reuse2d
Boosting RISC-V SoC performance for AI and ML applications
At around the same time, the open and configurable RISC-V instruction set architecture (ISA) is experiencing rapid adoption across diverse markets. This growth aligns with rising SoC complexity and ...
Design And Reuse2d
PolarFire Core devices streamline costs while retaining the market-leading power efficiency, security and reliability of classic PolarFire families
PolarFire Core devices are supported by Microchip’s Libero® SoC Design Suite, SmartHLS™ compiler, VectorBlox™ Accelerator SDK and Microchip’s Mi-V ecosystem of partner platforms for rapid RISC-V ...
Design And Reuse1d
Six HCLTech campuses in India receive the coveted TRUE Zero Waste Platinum Certification
HCLTech has announced that its campuses in Noida, Chennai, Bengaluru, Lucknow, Vijayawada and Madurai have been awarded the highest TRUE Zero Waste Certification, Platinum, by the Green Business ...